Example records of self-aligning masks for chip masks

 Examples of self-aligning chips masks

Wafer Scale Integration using CMOS chips for biomedical applications via self-aligned masking

Science.gov (United States)

Uddin Ashfaque; Milaninia Kaveh; Chen Chin-Hsuan. Theogarajan. Luke

2011-12-01

This paper presents a novel method for integrating small CMOS chip into a large-area substrate. The key component of the technique's success is the self-aligned masking CMOS chips based on. This allows you to make sockets from wafers which are no more than 5 Aum larger than each chip. The large area substrate and the chip are bonded to each other on a carrier, so the top surfaces of both components are flush. These unique characteristics allow for integration of macroscale components like microfluidics or leads. MEMS micromachining is possible after CMOS die wafer integration. A low-power integrated sensor chip for biosensing is embedded in a silicon substrate to demonstrate the potential of the technology. After the integration, the horizontal gap between the chip's large-area substrate and the chip was 4 Aum. The vertical displacement between them was 0.5 Aum. There are 104 interconnects that have been patterned using high-precision alignment. An electrical measurement has shown that the integration process does no affect the functionality.

An innovative micromachined shadow-mask system with gap control and self-alignment

International Nuclear Information System - (INIS)

Hong, Jung Moo; Zou Jun

2008-01-01

This paper presents a new micromachined shadow system that is capable of precise alignment and gap control between masks. The shadow-mask system comprises a silicon shadow and a silicon carrier with silicon cavities made with bulk micromachining. Matching pairs with steel spheres between the pyramidal cavities and shadow mask can easily achieve gap control and alignment of the substrate and shadow mask. Experimentally, the accuracy of the new shadow-mask system's layer-to–layer alignment has been measured using optical and atomic force microscopic methods. An organic thin-film transistor (OTFT), which uses pentacene for its semiconductor layer, has been successfully manufactured and tested using this shadow mask system.

For semiconductor processing, mask alignment system

Science.gov (United States)

Webb (Aaron P.); Carlson (Charles T.); Weaver (19 William T.); Grant (Christoph N.

2017-02-14

A mask alignment system to ensure a repeatable and precise alignment of ion implant masks and workpieces. The system comprises a mask frame that has a plurality or ion-implantation masks loosely attached to it. The mask frame has a plurality o of alignment cavities. Each mask has its own alignment cavity. The system also includes a platen to hold workpieces. The platen can have a number of mask alignment pins or frame alignment pins that engage the frame alignment cavities and mask alignment cavities. To ensure rough alignment between the workpieces and masks, the frame alignment cavities can be moved into alignment with the frame pins. After the mask alignment cavities have been moved into alignment with mask alignment pins, each mask can be adjusted to align with a workpiece. 640 paulson heads up poker chip set critical overview